Macrocycle for control in the controller

[rezabejd]

Originally Posted by tfreitass

Dear all,

]1) The communication between DCS controller signals related to control and FF devices in a H1 segment is acyclic or cyclic? Considering a single loop, I suppose that data sent by DCS controller (PID output) is acyclic and data received by DCS controller (BCALC) is cyclic. Is that correct?]

I think the answer is host-dependent and may still not reflect reality. On the system I use, control outputs show up as cyclic "publish" events (compel data) on the macrocycle schedule, but there's not any guarantee that the controller-resident PID has actually solved a new output at the time the H1 link master blasts out the (supposedly new) number. The H1 link master is not innately capable of "scheduling" the host-resident PID block.

Originally Posted by tfreitass

2) Considering the answer to item 01, how can I calculate the macrocycle (required macrocyle: FB processing + communication)? My assumption for a single loop is:

macrocycle = AI_processing + AI_publishSubscribe + AOprocessing + BCALC_publishSubscribe

"Required macrocycle" only depends on the field function block load (how many and how long for each) and the number of required "compel data" or publish events, plus some allocation for acyclic comms (recommendations vary). Control in host would typically add at least one more compel data that would usually be absent in the field (with PID solved in either the AO-containing device or the AI-containing device).

Originally Posted by tfreitass

3) How can I calculate the response time? By response time I mean, in a single loop example, the time between the transmitter receive a new input signal and actuator receive control signal related to this new input signal. My assumption, again for a single loop, is:

response_time = (2 x macrocycle) + DCS_controlProcessing + DCS_acyclicCommunication

The only meaningful (to me) study I've seen was done by some Emerson people in their flow lab. They had to prove the data empirically. Their Jim Cahill makes reference to it here. Maybe some nice Emerson person can upload the PDF to our thread?? The gist of it is, macrocycle and controller module execution did not predict response times.